In the evolution of integrated circuits in semiconductor technology, there has been a trend towards device scaling. Scaling or reducing the size increases circuit performance, primarily by increasing circuit speed, and also increases the functional complexity of the integrated circuits. The number of devices per integrated circuit (also referred to in the art as a chip or die) has increased throughout the years. When integrated circuits contained only a small number of devices per chip, the devices could be easily interconnected in a single level. However, the need to accommodate more devices and increased circuit speed has led to the use of multi-level or multi-layer interconnects.
In a multi-level interconnection system, the area needed by the interconnect lines is shared among two or more levels, which increases the active device fractional area, resulting in increased functional chip density. Implementing a multilevel interconnect process to a fabrication scheme increases the complexity of the manufacturing process. Typically, the active devices (e.g., the transistors, diodes, capacitors and other components) are manufactured in the lower layers of wafer processing. After the active devices are processed, the multilevel interconnects are usually formed. Hundreds or thousands of chips or die are typically manufactured on a single wafer. The die are separated after the manufacturing process is complete by sawing the die apart on scribe lines at edges of each die. The die are then individually packaged, or are packaged in multi-chip modules, as examples.
As semiconductor devices continue to shrink, various aspects of multilevel interconnect processes are challenged. The propagation delay of integrated circuits becomes limited by the large RC time delay of interconnection lines when minimum feature size is decreased below about 1 μm, for example. Therefore, the industry is tending towards the use of different materials and processes to improve multilevel interconnect implementations. In particular, the change in the conductive materials and insulating materials used in multilevel interconnect schemes is proving challenging and requires a change in a number of processing parameters.
For many years, the insulating material used to isolate conductive lines from one another was silicon dioxide. Silicon dioxide has a dielectric constant (k) of approximately 4.0 or greater, where the dielectric constant value k is based on a scale where 1.0 represents the dielectric constant of vacuum. However, now there is a trend in the semiconductor industry towards the use of low-dielectric constant materials (e.g., having a dielectric constant k of about 3.5 or less) for insulating materials.
Integrated circuit manufacturers are employing finer circuit widths, low dielectric constant (low-k) materials, and other technologies to make smaller and higher-speed semiconductor devices. Along with these advancements, the challenges of maintaining yield and throughput have also increased. Low-k materials tend to be weaker and less robust than the silicon dioxide that was used as a dielectric material in the past. As far as reliability is concerned, the low-k material near die corners has a tendency to crack/delamination, especially in the sawing process to separate the die from one another. The cracks tend to occur in a direction parallel to the wafer surface.
In general, the scribe lines are defined in areas of the multi-layer structure that are without a die circuit pattern and have a width of about 80 to 120 μm, depending on the dimensions of the die manufactured on the wafer. Furthermore, when at least one layer of the multi-layer structure is composed of a metal material with a high thermal expansion coefficient, the dimensional variation of the layer is sufficient to introduce high-level internal stress into the wafer in the area of the scribe line. Consequently, portions of the wafer around the scribe line suffer damage, such as peeling, delamination, or dielectric fracture. The types of scribe line damage mentioned above are usually observed when the multi-layer structure includes an inter-metal-dielectric layer of low dielectric constant (low-k).
The stress resulting from the sawing process causes serious peeling starting from near the test keys at the die corners. This results in delamination at the interface between the multiple layers at the die corners. Delamination impacts the reliability of the device, and contributes to production of stringers (residual materials) that interfere with further processing testing of the integrated circuit. It is not uncommon for stresses to crack a passivation film formed over the die corners during the sealing process of a resin mode package. If a low-k material is used near the guard ring corners, the crack issue becomes more serious and further reduces reliability.